package bus

import chisel3._
import chisel3.util._
import utils._

class CBusReq(dataBits:Int, addrBits:Int, beBits:Int = 4) extends Bundle{
    val addr    =   Output(UInt(addrBits.W))
    val we      =   Output(Bool())
    val be      =   Output(UInt(beBits.W))
    val wdata   =   Output(UInt(dataBits.W))
    val hprot   =   Output(UInt(2.W))

    def needSplit = {
        assert(beBits == 4, "CBus dataBits error")
        this.we & this.be(1) & this.be(2) & (~(this.be(0) & this.be(3))) // 0110 0111 1110
    }
}

class CBusResp(dataBits:Int) extends Bundle{
    val err     =   Output(Bool())
    val rdata   =   Output(UInt(dataBits.W))
}


class CBusReqWithMr(dataBits:Int, addrBits:Int) extends CBusReq(dataBits:Int, addrBits:Int){
    val mr    =   Output(Bool())
}

class CBus32Bundle(dataBits:Int, addrBits:Int) extends Bundle {
    val req = Decoupled(new CBusReq(dataBits, addrBits))  // valid=>req , ready=>gnt
    val resp = Flipped(Valid(new CBusResp(64))) // valid=>rvalid
}

class CBus64Bundle(dataBits:Int, addrBits:Int) extends Bundle {
    val req = Decoupled(new CBusReqWithMr(dataBits, addrBits))  // valid=>req , ready=>gnt
    val resp = Flipped(Valid(new CBusResp(64))) // valid=>rvalid
}